1. Field of the Invention
The present invention relates to the implementation of a monolithic rectifying bridge protected against overvoltages.
2. Discussion of the Related Art
Power components currently available for sale are implemented based on technologies in which the rear surface of the component is uniformly coated with a metallization in contact with the apparent semiconducting layers of this rear surface. With these types of technologies, it has been considered, up to now, that it was not possible to implement in monolithic form a component providing the functions of a medium or high power rectifying bridge protected against overvoltages, and such components are not available for sale.
Besides, French patent application 94/16011 filed on Dec. 30, 1994, by the applicant, entitled "Integrated power circuit", and incorporated herein by reference discloses a new concept of an integrated power circuit which enables monolithic assembly of many logic and power components in the same semi-conductor circuit. In order to achieve this result, this patent application notably teaches to appropriately use insulating layers formed on the rear surface of a component, the rear surface metallization being partly in contact with the rear surface semiconductor structures and being partly insulated by these insulating layers.
The use of the teachings of this patent application is extremely rich and enables implementation, in monolithic form, of many component assemblies which were previously implemented only as assemblies of discrete components.
Among the examples of application given in this patent application, there appear rectifying bridges protected against overvoltages.
FIG. 11A of this prior patent application, reproduced in FIG. 1, shows such a protected rectifying bridge including four rectifying diodes D1 to D4 and a double Shockley S. Diagrams equivalent to the diagram of FIG. 11A of this patent application are illustrated in FIGS. 11B and 11C, this last drawing being reproduced in FIG. 2. It should be noted that from a functional point of view, the diagram of FIG. 2 is strictly identical to that of FIG. 1. In FIGS. 1 and 2, terminals T1, T2 designate a.c. supply terminals and terminals T+ and T- designate d.c. voltage supply terminals.
Next, this prior patent application shows in its FIGS. 13A and 13B, reproduced in FIGS. 3A and 3B, a simplified example of implementation of the circuit illustrated in FIG. 11C (appended FIG. 2). In FIGS. 3A and 3B, exactly the same reference numbers as in FIGS. 13A and 13B of the prior patent application are kept and, to describe these drawings, reference will be made to this prior patent application.
It will only be noted that:
N-type substrate 1 is lightly doped,
regions 30 and 31 correspond to P-type isolating walls,
diode D2 and Shockley diode S2 are formed vertically in a first well,
diode D4 and Shockley diode S4 are formed vertically in a second well,
diodes D1 and D3 are formed laterally in a third well.
Diode D1 corresponds to PNN.sup.+ regions 52, 1, 54,
diode D3 corresponds to PNN.sup.+ regions 53, 1, 54,
diode D2 corresponds to PNN.sup.+ regions 42, 1, 50 and diode D4 to homologous regions,
Shockley diode S2 includes from its anode to its cathode PNN+PN regions 40, 1, 46, 42 and 44 and Shockley diode S4 includes homologous regions.
The structure described and schematically shown in FIGS. 3A and 3B gives satisfactory results.
However, in the field of semiconductor component fabrication, manufacturers generally desire to derive as little as possible from conventional and tested dies. Thus, when it is possible to avoid using technologies requiring to use a rear surface insulated layer, this solution is preferred.